As memory cell density increases, there is a continuing challenge to maintain sufficiently high storage capacitance despite decreasing cell area. One way of increasing cell capacitance is through three-dimensional cell capacitor structures, such as trenched or stacked capacitors.
Stacked capacitor DRAMs utilize either a buried bit line or a non-buried bit line structure. With buried bit line structures, bit lines are provided in close vertical proximity to the bit line contacts of the memory cell field effect transistors (FETs), and the cell capacitors are formed horizontally over the top of the word lines and bit lines. Buried bit line structures, sometimes referred to as capacitor-over-bit-line (COB) structures, are the subject of this invention.
Sim et al., "A New Planar Stacked Technology (PST) for Scaled and Embedded DRAMs," IEEE, IEDM 96-597-600 (1996), refers to a COB type DRAM structure made by a process of inserting a connecting layer between a storage node contact and a gate polysilicon layer. After formation of a tungsten damascene bit line, the storage node contact is opened and a polysilicon plug is formed by deposition and etch-back. Capacitors are formed by oxide etch selective to storage node hole formation, followed by polysilicon deposition and CMP for cylindrical capacitor definition. The cell plate is then patterned, followed by W-plug CMP and metalization.
M. Sakao et al., "A Capacitor-Over-Bit-Line (COB) Cell with a Hemispherical-Grain Storage Node for 64 Mb DRAMs," IEEE, IEDM 90-655-658 (1990), refers to a process for making a COB cell wherein, after opening a self-aligned contact to the active area, a polysilicon layer is formed as a local interconnect. After an insulating interlayer deposition, a bit line contact is opened and filled with a doped polysilicon plug. A polycide bit line is then formed, and an insulating interlayer is deposited on the bit line and planarized. After opening the capacitor contact, an HSG polysilicon storage node is formed and connected to the active area through the capacitor contact and local interconnect.
The goal of increasing or, at least, maintaining cell capacitance as cell size shrinks must be attained without resorting to processes that increase the number of masking, deposition, etch and other steps in the production process. This has a great impact on manufacturing costs, particularly the costs of photolithographic steps. High capital costs are associated with photolithographic equipment and more complex photo processing, in terms of more photo process steps per level, more equipment, and the use of expensive ultra clean room floor space. Defect density is inevitably increased with each additional photomasking layer and compromises yield and reliability. All photo layers also require a subsequent step, either implant or etch. These additional steps further add to manufacturing costs.
What is needed is a capacitor over bit line cell of reduced complexity that can be fabricated with a minimum of process steps.